1. Field of the Invention
The present invention relates to oscillators in the gigahertz range, and particularly to a high-frequency digitally controlled oscillator having an extended range of frequency operation.
2. Description of the Related Art
Many applications require the generation of high-speed clocks on-chip with minimal area and power consumption. Analog phase-locked loops (PLLs) can provide precise frequencies, but contain analog circuits and an analog filter that take up a large amount of chip space and are impossible to port from one fabrication process to another. All digital PLLs are more portable and have smaller area on chip. However, they require digitally controlled oscillators (DCOs) with monotonic behavior, fine frequency resolution, and good period linearity. Over the years, many DCOs have been proposed. Almost all of the reported DCOs use two stages for frequency tuning, including a coarse tuning stage and a fine tuning stage. This allows the DCO to have a large frequency range with fine resolution while using a minimal number of control bits. This, however, may also limit the maximum output frequency of the DCO.
Existing DCOs employ one or more techniques, including using current-starved inverters as delay stages, using inverters with switched shunt MOS capacitors, and using multiplexers to select the number of delay stages (path selection). Path selection is seldom used on its own due to its limited resolution, and is usually combined with other techniques. For shunt capacitors, some researchers use MOS varactors with differential drive due to their excellent linearity. This, however, requires a large number of delay stages due to the small capacitance of varactors. Pass gates may be used between inverter stages as digitally-controlled variable resistors, and Schmitt triggers may be used to re-construct the weakened signals. Although all these techniques work effectively to produce fine resolution and large frequency range with adequate linearity, they all suffer from a basic shortcoming, viz., limited maximum frequency. This is due to the fact that whatever technique is used to control the DCO's period, the elements that are used to control the delay around the DCO (series resistances, shunt capacitors, or selection multiplexers) always exist in the circuit and can't be physically eliminated at the highest DCO frequency. Also, switches (NMOS, PMOS or transmission gates) controlling these elements introduce significant parasitic capacitances, reducing the DCO's maximum attainable frequency further. These two issues lead to a basic trade off in all existing DCOs. In order to increase the resolution and/or frequency range, more delay elements have to be added, which reduces the DCO's intrinsic (maximum) frequency. Also, in order to increase the range, the range of values of the binary-weighted resistors or capacitors (used as delay control elements in the DCO) must be increased. This causes matching problems and can lead to non-monotonic DCO frequency characteristics at some control code words. This also forces designers to use the highly non-linear MOS capacitors to be able to get large capacitance values in reasonable silicon area.
Thus, a high-frequency digitally controlled oscillator solving the aforementioned problems is desired.